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Título: Realistic detection of interconnect opens under process variations
Autores: JESUS MORENO MORENO
Fecha: 2012-06
Publicador: INAOE
Fuente:
Tipo: info:eu-repo/semantics/doctoralThesis
info:eu-repo/semantics/acceptedVersion
Tema: info:eu-repo/classification/Circuitos/Circuit CAD
info:eu-repo/classification/Pruebas estadísticas/Statistical testing
info:eu-repo/classification/Sitios de prueba de áreas abiertas/Open area test sites
info:eu-repo/classification/Confiabilidad/Reliability
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
Descripción: CMOS IC scaling has provided significant improvements in electronic circuit performance. Advances in test methodologies to deal with new failure mechanisms and nanometer issues are required. Interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. In nanometer process, variability is predominant and considering only nominal value of parameters is not realistic. In this thesis, a model for computing a realistic coverage of via open defects that takes into account the process variability is proposed. Spatial and parametric correlation between device parameters, spatial correlation between interconnect parameters, random dopant fluctuation and trapped gate charge are considered. Furthermore, these factors can also influence the detection of the defect. In addition, the detection capability of Low Voltage Testing for interconnect opens, considering process variations, is evaluated using a statistical model. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS benchmark circuits. The proposed detection probability evaluation together with a test methodology to generate favorable logic conditions at the coupling lines can allow a better test quality leading to higher product reliability.
Idioma: eng