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Título: Hardware architecture for pairing-based cryptography
Autores: EDUARDO CUEVAS FARFAN
Fecha: 2013-11
Publicador: INAOE
Fuente:
Tipo: info:eu-repo/semantics/masterThesis
info:eu-repo/semantics/acceptedVersion
Tema: info:eu-repo/classification/Criptografía/Cryptography
info:eu-repo/classification/Seguridad de los datos/Security of data
info:eu-repo/classification/Aritmética digital/Digital arithmetic
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/12
info:eu-repo/classification/cti/1203
Descripción: Bilinear pairings over elliptic curves are an emerging research field in cryptography. First cryptographic protocols based on bilinear pairings were proposed by the year 2000 and currently they are not standardized. The computation of bilinear pairings relies on arithmetic over finite fields. The bilinear pairing is the most time-consuming in Pairing-based cryptosystems which has motivated its implementation in dedicated hardware. In the literature, several works have focused in the design of custom hardware architectures for eficient implementation of this arithmetic, but in a non-standardized environment a flexible design is preferred in order to support changes in the specifications. This thesis presents the design and implementation of a novel programmable cryptoprocessor for computing bilinear pairings over binary fields in FPGA, which is able to support difierent algorithms and corresponding parameters such as the elliptic curve, the tower field and the distortion map. The results show that high flexibility is achieved by the proposed cryptoprocessor at a competitive timing and area usage when it is compared to custom designs for pairings defined over singular/supersingular elliptic curves at a 128-bit security level.
Idioma: eng