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Título: A low cost advance encryption standard (AES) co-processor implementation
Autores: Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
Fecha: 2008-09-24
2008
Publicador: Unversidad Nacional de La Plata
Fuente:


Tipo: Articulo
Articulo
Tema: AES; cryptographic architectures; FPGA design; specialized architectures; VLSI design
Ciencias Informáticas
Informática
Aplicación informática
Encriptación de datos
Descripción: The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
Idioma: Inglés