| Título: | Low Power Schmitt Trigger |
| Autores: |
Kundra, Swati Soni, Priyanka |
| Fecha: | 2012-01-25 |
| Publicador: | Innovative systemas design and engineering |
| Fuente: |
 |
| Tipo: |
info:eu-repo/semantics/article Peer-reviewed Article info:eu-repo/semantics/publishedVersion |
| Tema: | No aplica |
| Descripción: | The Schmitt Trigger is a comparator circuit that incorporates positive feedback. Noise is being ignored by CMOS Schmitt Trigger as the hysteresis in a Schmitt Trigger circuit offers a better noise margin and noise stable operation. And the simulation has been done on Tanner EDA tool at TSMC 130nm technology with 1 V supply voltage. TSPICE simulation results of the circuit confirm the effectiveness of the approach. Proposed Schmitt Trigger is designed by using less transistor count and a capacitor which results in less average power consumption with decrease in area. Delay is also decreased by using only one PMOS as because delay is more concentrated to PMOS due to less mobility of PMOS compare to NMOS. Keywords: CMOS Schmitt Trigger, Delay, Low power consumption |
| Idioma: | Inglés |